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DS1500
Y2KC Watchdog RTC with NV Control
www.maxim-ic.com
FEATURES
BCD-coded century, year, month, date, day, hours, minutes, and seconds with automatic leap-year compensation valid up to the year 2100 Programmable watchdog timer and real-time clock (RTC) alarm Century register; Y2K-compliant RTC Automatic battery backup and write protection to external SRAM +5V operation Precision power-on reset Power-control circuitry supports system power-on from date/day/time alarm or key closure 256 bytes user NV RAM Auxiliary battery input Accuracy is better than 1 minute/month at +25C Day of week/date alarm register Battery voltage-level indicator flags Optional industrial temperature range: -40C to +85C
PIN ASSIGNMENT (Top View)

DS1500
Package dimension information can be found at:
http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm
ORDERING INFORMATION
DS1500XXX blank Commercial Temp. Range N Industrial Temp. Range E Y 32-Pin TSOP 5V Operation
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: http://www.maxim-ic.com/errata. 1 of 24 041502
DS1500
PIN DESCRIPTION
VCCI - Supply Voltage A0 to A4 - Address Inputs DQ0 to DQ7 - Data I/O CS - RTC Chip-Select Input OE - RTC Output-Enable Input WE - RTC Write-Enable Input IRQ - Interrupt Output (Open Drain) PWR - Power-On Output (Open Drain) RST - Reset Output (Open Drain)
KS
SQW VBAT VBAUX
CEI CEO
VCCO X1, X2 GND
- Kickstart Input - Square-Wave Output - Backup-Battery Supply - Auxiliary-Battery Supply - RAM Chip-Enable Input - RAM Chip-Enable Output - RAM Power-Supply Output - 32.768kHz Crystal Pins - Ground
DESCRIPTION
The DS1500 is a full-function, year 2000-compliant real-time clock/calendar (RTC) with an alarm, watchdog timer, power-on reset, battery monitors, 256 bytes of on-board NV SRAM, NV control for backing up an external SRAM, and a 32.768kHz output. User access to all registers within the DS1500 is accomplished with a bytewide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for day of month and leap year are made automatically. The RTC registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. When the crystal oscillator is turned on, the internal set of registers are continuously updated; this occurs regardless of external register settings to guarantee that accurate RTC information is always maintained. The DS1500 contains its own power-fail circuitry that automatically deselects the device when the VCCI supply falls below a power-fail trip point. This feature provides a high degree of data security during unpredictable system operation caused by low VCCI levels. An external SRAM can be made nonvolatile by using the VCCO and CEO pins. Nonvolatile control of the external SRAM is analogous to that of the RTC registers. When VCCI slews down during a power fail, CEO is driven to an inactive level regardless of CEI . This write protection occurs when VCCI is less than the power-fail trip point. The DS1500 has interrupt ( IRQ ), power control ( PWR ), and reset ( RST ) outputs that can be used to control CPU activity. The IRQ interrupt or RST outputs can be invoked as the result of a time-of-day alarm, CPU watchdog alarm, or a kickstart signal. The DS1500 power-control circuitry allows the system to be powered on by an external stimulus, such as a keyboard or by a time and date (wake-up) alarm. The PWR output pin can be triggered by one or either of these events, and can be used to turn on an external power supply. The PWR pin is under software control, so that when a task is complete, the system power can then be shut down. The DS1500 power-on reset can be used to detect a system power-down or failure and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used for this function. The DS1500 is a clock/calendar chip with the features described above. An external crystal and battery are the only components required to maintain time-of-day and memory status in the absence of power.
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DS1500
Figure 1. BLOCK DIAGRAM
VCCI
Table 1. RTC OPERATING MODES
VCCI
CS OE WE
VIH VCCI > VPF VIL VIL VIL VSO < VCCI < VPF VCCI < VSO < VPF X X
X X VIL VIH X X
X VIL VIH VIH X X
DQ0-DQ7 High-Z DIN DOUT High-Z High-Z High-Z
A0-A4 X AIN AIN AIN X X
MODE Deselect Write Read Read Deselect Data Retention
POWER Standby Active Active Active CMOS Standby Battery Current
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RTC DATA READ MODE
The DS1500 is in the read mode whenever CS (chip select) is low and WE (write enable) is high. The device architecture allows ripple-through access to any valid address location. Valid data is available at the DQ pins within tAA (address access) after the last address input is stable, provided that CS and OE access times are satisfied. If CS or OE access times are not met, valid data is available at the latter of chip-enable access (tCSA) or at output-enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CS and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CS and OE remain valid, output data remains valid for output-data hold time (tOH) but then goes indeterminate until the next address access (Table 1).
RTC DATA WRITE MODE
The DS1500 is in the write mode whenever WE and CS are in their active state. The start of a write is referenced to the latter occurring transition of WE or CS . The addresses must be held valid throughout the cycle. CS or WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to a high-to-low transition on WE , the data bus can become active with read data defined by the address inputs. A low transition on WE then disables the outputs tWEZ after WE goes active (Table 1).
DATA RETENTION MODE
The 5V device is fully accessible and data can be written and read only when VCCI is greater than VPF. However, when VCCI falls below the power-fail point VPF (point at which write protection occurs), the internal clock registers and SRAM are blocked from any access. While in the data retention mode, all inputs are "don't cares" and outputs go to a high-Z state, with the exception of VCCO, CEO , and the possible exception of KS , PWR , SQW, and RST . When VCCI falls below the greater of VBAT or VBAUX, device power is switched from the VCCI pin to the greater of VBAT or VBAUX. RTC operation and external SRAM data are maintained from the battery until VCCI is returned to nominal levels (Table 1). All control, data, and address signals must be no more than 0.3V above VCCI.
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DS1500
AUXILIARY BATTERY
The VBAUX input is provided to supply power from an auxiliary battery for the DS1500 kickstart and square-wave output features in the absence of VCCI. This power source must be available to use these auxiliary features when no VCCI is applied to the device. This auxiliary battery can be used as the primary backup power source for maintaining the clock/calendar and external SRAM. This occurs if the VBAT pin is at a lower voltage than VBAUX. If the DS1500 is to be backed-up using a single battery with the auxiliary features enabled, then VBAUX should be used and connected to VBAT. If VBAUX is not to be used, it should be grounded.
POWER ON RESET
A temperature-compensated comparator circuit monitors the level of VCCI. When VCCI falls to the powerfail trip point, the
RST
signal (open drain) is pulled low. When VCCI returns to nominal levels, the
RST
signal continues to be pulled low for a period of 40ms to 200ms. The power-on reset function is independent of the RTC oscillator and therefore operational whether or not the oscillator is enabled.
CLOCK OSCILLATOR CONTROL
The clock oscillator can be stopped at any time. To increase the shelf life of a backup lithium-battery source, the oscillator can be turned off to minimize current drain from the battery. The EOSC bit is used to control the state of the oscillator, and must be set to a 0 for the oscillator to function.
READING THE CLOCK
When reading the clock and calendar data, it is recommended to halt updates to the external set of doublebuffered RTC registers. This puts the external registers into a static state allowing data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state. External updates are halted when a 0 is written into the read (TE) bit of control register B (0Fh). As long as a 0 remains in the control register B (TE) bit, updating is halted. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command was issued. Normal updates to the external set of registers resume within 1 second after the (TE) bit is set to a 1.
SETTING THE CLOCK
It is also recommended to halt updates to the external set of double-buffered RTC registers when writing to the clock. The TE bit should be used as described above before loading the RTC registers with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the TE bit to a 1 transfers the values written to the internal RTC registers and allows normal operation to resume.
CLOCK ACCURACY
A standard 32.768kHz quartz crystal should be directly connected to the DS1500 X1 and X2 oscillator pins. The crystal selected for use should have a specified load capacitance (CL) of either 6pF or 12.5pF, and the crystal select (CS) bit set accordingly. For more information about crystal selection and crystal layout considerations, please consult Application Note 58, "Crystal Considerations with Dallas Real-Time
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DS1500
Clocks." The DS1500 can also be driven by an external 32.768kHz oscillator. In order to achieve lowpower operation when using an external oscillator, it may be necessary to connect the X1 pin to the external oscillator signal through a series connection consisting of a resistor and a capacitor. A typical configuration consists of a 1.0Meg resistor in series with a 100pF ceramic capacitor. When using an external oscillator the X2 pin must be left open. Accuracy of DS1510 is better than 1 min/month at +25C.
USING THE CLOCK ALARM
The alarm settings and control reside within registers 08h to 0Bh (Table 3). The TIE bit and alarm mask bits AM1 to AM4 must be set as described below for the IRQ or PWR outputs to be activated for a matched alarm condition. The alarm can be programmed to activate on a specific day of the month, day of the week, or repeat every day, hour, minute, or second. It can also be programmed to go off while the DS1500 is in the batterybacked state of operation to serve as a system wake-up. Alarm mask bits AM1 to AM4 control the alarm mode. Table 2 shows the possible settings. Configurations not listed in the table default to the once-persecond mode to notify the user of an incorrect alarm setting. When the RTC register values match alarm register settings, the time-of-day/date alarm flag TDF bit is set to a 1. Once the TDF flag is set, the TIE bit enables the alarm to activate the IRQ pin. The TPE bit enables the alarm flag to activate the PWR pin. The alarm functions on VCC, VBATT, and VBAUX.
Table 2. ALARM MASK BITS
DY/DT X X X X 0 1 AM4 1 1 1 1 0 0 AM3 1 1 1 0 0 0 AM2 1 1 0 0 0 0 AM1 1 0 0 0 0 0 ALARM RATE Once per second When seconds match When minutes and seconds match When hours, minutes, and seconds match When date, hours, minutes, and seconds match When day, hours, minutes, and seconds match
USING THE WATCHDOG TIMER
The watchdog timer can be used to restart an out-of-control processor. The watchdog timer is user programmable in 10ms intervals ranging from 0.01 seconds to 99.99 seconds. The user programs the watchdog timer by setting the desired amount of time-out into the two BCD watchdog registers (Address 0Ch and 0Dh). For example, writing 60h in the watchdog register 0Ch and 00h to watchdog register 0Dh sets the watchdog time-out to 600ms. If the processor does not access the timer with a write within the specified period, both the watchdog flag (WDF) and the interrupt request flag (IRQF) are set. If the watchdog enable bit (WDE) is enabled, then either IRQ or RST go active depending on the state of the watchdog steering bit (WDS). The watchdog is reloaded and restarted whenever the watchdog times out. The WDF bit is set to a 1 regardless of the state of WDE to serve as an indication to the processor that a watchdog time out has occurred.
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The watchdog timer is reloaded when the processor performs a write of the watchdog registers. The timeout period then starts over. The watchdog timer is disabled by writing a value of 00h to both watchdog registers. The watchdog function is automatically disabled upon power-up. The following summarizes the configurations in which the watchdog can be used: 1) WDE = 0 and WDS = 0: WDF is set. 2) WDE = 0 and WDS = 1: WDF is set. 3) WDE = 1 and WDS = 0: WDF and IRQF are set, and the IRQ pin is pulled low. 4) WDE = 1 and WDS = 1: WDF is set, the RST pin is pulled low for a duration of 40ms to 200ms, and WDE is reset to 0.
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CLEARING IRQ AND FLAGS
The time-of-day/date alarm flag (TDF), watchdog flag (WDF), and interrupt request flag (IRQF) are cleared by reading the flag register (0EH) as shown in Figures 2a, 2b, and 2c. The address must be stable for a minimum of 15ns (tIRQZ). After the tIRQZ requirement is met, either a change in address (Figure 2a), a rising edge of OE (Figure 2b), or a rising edge of CS causes the flags to be cleared. The IRQ pin goes inactive after the IRQF flag is cleared.
Figure 2a. IRQ AND FLAG WAVEFORMS (ADDRESS RELATED)
Figure 2b. IRQ AND FLAG WAVEFORMS ( OE RELATED)
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DS1500
Figure 2c. IRQ AND FLAG WAVEFORMS ( CS RELATED)
WAKE-UP/KICKSTART
The DS1500 incorporates a wake-up feature, which powers on at a predetermined date by activating the PWR output pin. In addition, the kickstart feature allows the system to be powered up in response to a low-going transition on the KS pin, without operating voltage applied to the VCCI pin. As a result, system power can be applied upon such events as key closure, or a modem ring-detects signal. In order to use either the wake-up or the kickstart features, the DS1500 must have an auxiliary battery connected to the VBAUX pin and the oscillator must be running. The wake-up feature is controlled through the time-of-day/date power-enable bit (TPE). Setting TPE to 1 enables the wake-up feature. Writing TPE to 0 disables the wake-up feature. Similarly, the kickstart feature is controlled through the kickstart interrupt enable bit (KIE). If the wake-up feature is enabled, while the system is powered down (no VCCI voltage), the clock/calendar monitors the current day or date for a match condition with day/date alarm register (0Bh). In conjunction with the day/date alarm register, the hours, minutes, and seconds alarm bytes in the clock-calendar register map (02h, 01h, and 00h) are also monitored. As a result, a wake-up occurs at the day or date and time specified by the day/date, hours, minutes, and seconds alarm-register values. This additional alarm occurs regardless of the programming of the TIE bit. When the match condition occurs, the PWR pin is automatically driven low. This output can be used to turn on the main system power supply, which provides VCCI voltage to the DS1500 as well as the other major components in the system. Also, at this time, the time-of-day/date alarm flag is set, indicating that a wake-up condition has occurred. If the kickstart feature is enabled with the KSE bit and VBAUX is present, while VCCI is low, the KS input pin is monitored for a low-going transition of minimum pulse width tKSPW. When such a transition is detected, the PWR line is pulled low, as it is for a wake-up condition. Also at this time, the kickstart flag
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(KSF) is set, indicating that a kickstart condition has occurred. The must not be allowed to float.
KS
input pin is always enabled and
The timing associated with both the wake-up and kickstarting sequence is illustrated in Figure 7. The timing associated with these functions is divided into five intervals, labeled 1 to 5 on the diagram. The occurrence of either a kickstart or wake-up condition causes the PWR pin to be driven low, as described above. During Interval 1, if the supply voltage on the VCCI pin rises above the greater of VBAT or VPF before the power-on timeout period (tPOTO) expires, then PWR remains at the active-low level. If VCCI does not rise above the greater of VBAT or VPF in this time, then the PWR output pin is turned off and returns to its high-impedance level. In this event, the IRQ pin also remains tristated. The interrupt flag bit (either TDF or KSF) associated with the attempted power-on sequence remains set until cleared by software during a subsequent system power-on. If VCCI is applied within the time-out period, then the system power-on sequence continues as shown in Intervals 2 to 5 in the timing diagram. During Interval 2, PWR remains active and IRQ is driven to its active-low level, indicating that either TDF or KSF was set in initiating the power-on. In the diagram, KS is assumed to be pulled up to the VBAUX supply. Also at this time, the PAB bit is automatically cleared to 0 in response to a successful power-on. The PWR line remains active as long as the PAB remains cleared to 0. At the beginning of Interval 3, the system processor has begun code execution and clears the interrupt condition of TDF and/or KSF by writing 0's to both of these control bits. As long as no other interrupt within the DS1500 is pending, the IRQ line is taken inactive once these bits are reset, and execution of the application software can proceed. During this time, both the wake-up and kickstart functions can be used to generate status and interrupts. TDF is set in response to a day/date, hours, minutes, and seconds match condition. KSF is set in response to a low-going transition on KS . If the associated interrupt-enable bit is set (TDE and/or KIE), then the IRQ line is driven low in response to enabled event. In addition, the other possible interrupt sources within the DS1500 can cause IRQ to be driven low. While system power is applied, the on-chip logic always attempts to drive the PWR pin active in response to the enabled kickstart or wake-up condition. This is true even if PWR was previously inactive as the result of power being applied by some means other than wake-up or kickstart. The system can be powered down under software control by setting the PAB bit to a 1. This causes the open-drain PWR pin to be placed in a high-impedance state, as shown at the beginning of Interval 4 in the timing diagram. As VCCI voltage decays, the IRQ output pin is placed in a high-impedance state when VCCI goes below VPF. If the system is to be again powered on in response to a wake-up or kickstart, then both the TDF and KSF flags should be cleared, and TPE and/or KIE should be enabled prior to setting the PAB bit.
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During Interval 5, the system is fully powered down. Battery backup of the clock calendar and NV RAM is in effect and IRQ is tristated, and monitoring of wake-up and kickstart takes place. If PRS =1, PWR stays active; otherwise, if PRS = 0, PWR is tristated.
SQUARE-WAVE OUTPUT
The square-wave output is enabled and disabled through the E32K bit. If the square wave is enabled ( E32K = 0) and the oscillator is running, then a 32.768kHz square wave is output on the SQW pin. If the battery-backup 32kHz-enable bit (BB32) is enabled, and voltage is applied to VBAUX, then the 32.768kHz square wave is output on the SQW pin in the absence of VCCI.
BATTERY MONITOR
The DS1500 constantly monitors the battery voltage of the backup-battery sources (VBAT and VBAUX). The battery low flags VRT1 and VRT2 are set to a 1 if the battery voltage on VBAT and VBAUX are less than 2.5V (typical); otherwise, VRT1 and VRT2 are a 0. VRT1 monitors VBAT and VRT2 monitors VBAUX.
POWER-UP DEFAULT STATES
These bits are set upon power-up:
EOSC
= 0,
E32K
= 0, TIE = 0, KIE = 0, WDE = 0, and WDS = 0.
256 x 8 EXTENDED RAM
The DS1500 provides 256 x 8 of on-chip SRAM, which is controlled as nonvolatile storage sustained from a lithium battery. On power-up, the RAM is taken out of write-protect status by an internal signal. Access to the SRAM is controlled by two on-chip latch registers. One register is used to hold the SRAM address; the other is used to hold read/write data. The SRAM address space is from 00h to FFh. The 8-bit address of the RAM location to be accessed must be loaded into the extended RAM address register located at 10h. Data in the addressed location can be read by performing a read operation from location 13h, or written-to by performing a write operation to location 13h. Data in any addressed location can be read or written repeatedly with changing the address in location 10h. To read or write consecutive extended RAM locations, a burst mode feature can be enabled to increment the extended RAM address. To enable the burst mode feature, set the BME bit to a 1. With burst mode enabled, write the extended RAM starting address location to register 10h. Then read or write the extended RAM data from/to register 13h. The extended RAM address locations are automatically incremented on the rising edge of OE , WE , or CS only when register 13h is being accessed. Refer to the Burst Mode Timing Waveform (Figure 5) section. The address pointer wraps around after the last address is accessed.
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Table 3. DS1500 REGISTER MAP
DATA Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH VRT1 TE AM1 AM2 AM3 AM4 0 DY/DT B7 0 0 0 0 0
EOSC
BCD B3 B2 B1 B0 Function Seconds Minutes Hours Day Date Month Year Century Alarm Seconds Alarm Minutes Alarm Hours Alarm Day/Date Watchdog Watchdog IRQF WDS Control A Control B RAM ADDR LSB 00 to FF Range 00 to 59 00 to 59 00 to 23 1-7 01 to 31 01 to 12 00 to 99 00 to 39 00 to 59 00 to 59 00 to 23 1 to 7/ 1 to 31 00 to 99 00 to 99
B6
B5 10 SECONDS 10 MINUTES
B4
SECONDS MINUTES HOUR 0 DAY DATE MONTH YEAR CENTURY SECONDS MINUTES HOUR DAY/DATE 0.01 SECOND SECOND PAB TPE TDF TIE KSF KIE WDF WDE
0 0 0
E32K
10 HOURS 0 10 DATE BB32 10 MO 0
10 YEAR 10 CENTURY 10 SECONDS 10 MINUTES 10 HOURS 10 DATE
0.1 SECOND 10 SECOND VRT2 CS PRS BME
EXTENDED RAM ADDRESS RESERVED RESERVED EXTENDED RAM DATA RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
RAM DATA
00 to FF
0 = "0" and are read only
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Note: Unless otherwise specified, the state of the control/RTC/SRAM bits in the DS1500 is not defined upon initial power application; the DS1500 should be properly configured/defined during initial configuration.
CONTROL REGISTERS
The controls and status information for the features offered by the DS1500 are maintained in the following register bits:
EOSC - Oscillator Start/Stop Bit (05H Bit 7) This bit is used to turn the oscillator on and off. 1 - oscillator off 0 - oscillator on E32K - Enable 32.768kHz Output (05H Bit 6) This bit, when written to a 0, enables the 32.768kHz oscillator frequency to be output on the SQW pin if the oscillator is running.
BB32 - Battery-Backup 32kHz-Enable Bit (05H Bit 5) When the BB32 bit is written to a 1, it enables a 32kHz signal to be output on the SQW pin while the part is in battery-backup mode if voltage is applied to VBAUX. AM1 to AM4 - Alarm Mask Bits (08H Bit 7; 09H Bit 7; 0AH Bit 7; 0BH Bit 7) Bit 7 of registers 08h to 0Bh contains an alarm mask bit, AM1 to AM4. These bits, in conjunction with the TIE described later, allow the IRQ output to be activated for a matched-alarm condition. The alarm can be programmed to activate on a specific day of the month, day of the week, or repeat every day, hour, minute, or second. Table 2 shows the possible settings for AM1 to AM4 and the resulting alarm rates. Configurations not listed in the table default to the once-per-second mode to notify the user of an incorrect alarm setting. DY/DT - Day/Date Bit (0BH Bit 6) The DY/DT bit controls whether the alarm value stored in bits 0 to 5 of 0BH reflects the day of the week or the date of the month. If DY/DT is written to a 0, the alarm is the result of a match with the date of the month. If DY/DT is written to a 1, the alarm is the result of a match with the day of the week. VRT1 - Valid RAM and Time Bit 1 (0EH Bit 7) VRT2 - Valid RAM and Time Bit 2 (0EH Bit 6) These status bits give the condition of any batteries attached to the VBAT or VBAUX pins. The DS1500 constantly monitors the battery voltage of the backup-battery sources (VBAT and VBAUX). The VRT1 and VRT2 bits are set to a 1 if the battery voltage on VBAT and VBAUX are less than 2.5V (typical); otherwise, VRT1 and VRT2 bits are a 0. VRT1 reflects the condition of VBAT with VRT2 reflecting VBAUX. If either bit is read as a 0, the voltage on the respective pin is inadequate to maintain the RAM memory or clock functions. PRS - Reset Select Bit (0EH Bit 5) When set to a 0, the PWR pin is set high-Z when the DS1500 goes into power fail. When set to a 1, the PWR pin remains active upon entering power fail.
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PAB - Power Active Bar Control Bit (0EH Bit 4) When this bit is 0, the PWR pin is in the active-low state. When this bit is 1, the PWR pin is in the highimpedance state. This bit can be written to a 1 or 0 by the user. If either WF and WIE = 1 or KF and KSE = 1, the PAB bit is cleared to a 0. TDF - Time-of-Day/Date Alarm Flag (0EH Bit 3) A 1 in the TDF bit indicates that the current time has matched the alarm time. If the TIE bit is also a 1, the IRQ pin goes low and a 1 appears in the IRQF bit. KSF - Kickstart Flag (0 EH Bit 2) This bit is set to a 1 when a kickstart condition occurs or when the user writes it to a 1. This bit is cleared by writing it to a 0. WDF - Watchdog Flag (0 EH Bit 1) If the processor does not access the DS1500 with a write within the period specified in addresses 0CH and 0DH, the WDF bit is set to a 1. WDF is cleared by writing it to a 0. IRQF - Interrupt Request Flag (0 EH Bit 0) The interrupt request flag (IRQF) bit is set to a 1 when one or more of the following are true: TDF = TIE = 1 KSF = KIE = 1 WDF = WDE = 1 i.e., IRQF = (TDF x TIE) + (KSF x KIE) + (WDF x WDE) Any time the IRQF bit is a 1, the IRQ pin is driven low. TE - Transfer Enable Bit (0 FH Bit 7) When the TE bit is a 1, the update transfer functions normally by advancing the counts once per second. When the TE bit is written to a 0, any update transfer is inhibited and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be executed in a similar manner. TE is a read/write bit that is not modified by internal functions of the DS1500. CS - Crystal Select Bit (0 FH Bit 6) When CS is set to a 0, the oscillator is configured for operation with a crystal that has a 6pF specified load capacitance. When CS = 1, the oscillator is configured for a 12.5pF crystal. CS is disabled in the DS1510 module and should be set to CS = 0. BME - Burst-Mode Enable Bit (0 FH Bit 5) The burst-mode enable bit allows the extended user RAM address registers to automatically increment for consecutive reads and writes. When BME is set to a 1, the automatic incrementing is enabled; when BME is set to a 0, the automatic incrementing is disabled.
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TPE - Time-of-Day/Date Alarm Power-Enable Bit (0 FH Bit 4) The wake-up feature is controlled through the TPE bit. When the TDF flag bit is set to a 1, if TPE is a 1, the PWR pin is driven active. Therefore, setting TPE to 1 enables the wake-up feature. Writing a 0 to TPE disables the wake-up feature. TIE - Time-of-Day/Date Alarm Interrupt-Enable Bit (0 FH Bit 3) The TIE bit allows the TDF flag to assert an interrupt. When the TDF flag bit is set to a 1, if TIE is a 1, the IRQF flag bit is set to a 1. Writing a 0 to the TIE bit prevents the TDF flag from setting the IRQF flag. KIE - Kickstart Enable-Interrupt Bit (0 FH Bit 2) When VCCI voltage is absent and KIE is set to a 1, the PWR pin is driven active-low when a kickstart condition occurs ( KS pulsed low), causing the KSF bit to be set to 1. When VCCI is then applied, the IRQ pin is also driven low. If KIE is set to 1 while system power is applied, both IRQ and PWR are driven low in response to KSF being set to 1. When KIE is cleared to a 0, the KSF bit has no affect on the PWR or IRQ pins. WDE - Watchdog Enable Bit (0 FH Bit 1) When WDE is set to a 1, the watchdog function is enabled, and either the IRQ pin or RST pin is pulled active based on the state of the WDS bit. WDS - Watchdog Steering Bit (0 FH Bit 0) If WDS is a 0 when the WDF bit is set to a 1, the IRQ pin is pulled low. If WDS is a 1 when WDF is set to a 1, the watchdog outputs a negative pulse on the RST output for 40ms to 200ms, and the IRQF flag is set when the watchdog times out. The WDE bit is reset to a 0 immediately after RST goes active.
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ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground Commercial Operating Temperature Range Industrial Operating Temperature Range Storage Temperature Range Soldering Temperature Range -0.5V to +6.0V 0C to +70C -40C to +85C -55C to +125C See IPC/JEDEC J-STD-020A
* This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
OPERATING RANGE
RANGE Commercial Industrial TEMP. RANGE 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Power-Supply Voltage Logic 1 Voltage All Inputs VCCI = 5V 10% Logic 0 Voltage All Inputs VCCI = 5V 10% Battery Voltage Auxiliary-Battery Voltage SYMBOL VCCI VIH VIL VBAT VBAUX MIN 4.5 2.2 -0.3 2.5 2.5 TYP 5.0
(Over the operating range)
MAX 5.5 VCCI + 0.3 0.8 3.7 5.3 UNITS V V V V V NOTES 1 1 1 1 1
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DS1500
DC ELECTRICAL CHARACTERISTICS (Over the operating range; VCCI = 5.0V 10%)
PARAMETER Active Supply Current TTL Standby Current ( CS = VIH) CMOS Standby Current ( CS VCCI - 0.2V) Battery Current, Oscillator On SYMBOL ICC ICC1 ICC2 IBAT1 IBAT2 IIL IOL VOH VOL1 VOL2 VCCO1 ICCO1 VPF VSO VCCO2 ICCO2 VBAT 0.3 50 4.25 VBAT, VBAUX VCCI - 0.3 85 4.50 -1 -1 2.4 0.4 0.4 MIN TYP MAX 15 5 5 1.0 0.1 1 1 UNITS mA mA mA mA mA mA mA V V V V mA V V V mA 1 1 1, 3 7 7 1 1, 4 8 8 NOTES 2 2 2 9 9
Battery Current, Oscillator Off Input-Leakage Current (Any Input) Output-Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) Output Logic 0 Voltage IOUT = 2.1mA, DQ0-7 Outputs, CEO IOUT = 7.0mA, IRQ , PWR , and RST Outputs Output Voltage Output Current Write-Protection Voltage Battery-Switchover Voltage Output Voltage Output Current
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DS1500
AC OPERATING CHARACTERISTICS (Over the operating range; VCCI = 5.0V 10%)
PARAMETER Read Cycle Time Address Access Time CS to DQ Low-Z CS Access Time CS Data Off Time OE to DQ Low-Z OE Access Time OE Data Off Time Output Hold from Address Write Cycle Time Address Setup Time WE Pulse Width CS Pulse Width Data Setup Time Data Hold Time Address Hold Time WE Data Off Time Write Recovery Time CEI to CEO Propagation Delay SYMBOL tRC tAA tCSL tCSA tCSZ tOEL tOEA tOEZ tOH tWC tAS tWEW tCSW tDS tDH tAH tWEZ tWR tCEPD MIN 70 5 70 25 5 35 25 5 70 0 50 55 30 0 0 25 5 10 TYP MAX 70 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES
10 10 10 10
10
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DS1500
Figure 3. WRITE CYCLE TIMING, WRITE ENABLE-CONTROLLED
Figure 4. WRITE CYCLE TIMING, CHIP ENABLE-CONTROLLED
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DS1500
BURST MODE TIMING CHARACTERISTICS
PARAMETER Pulse Width, OE , WE , or CS High Pulse Width,
OE , WE ,
SYMBOL PWHIGH PWLOW
MIN TBD TBD
TYP
MAX
(VCCI = 5.0V 10%)
UNITS ns ns
NOTES
or
CS
Low
BURST MODE TIMING CHARACTERISTICS
PARAMETER Pulse Width, OE , WE , or CS High Pulse Width,
OE , WE ,
SYMBOL PWHIGH PWLOW
MIN TBD TBD
TYP
MAX
(VCCI = 3.3V 10%)
UNITS ns ns
NOTES
or
CS
Low
Figure 5. BURST MODE TIMING WAVEFORM
A 0-A 4 13h P W LO W P W H IG H
OE
, WE ,
or CS
DQ0-DQ7
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DS1500
POWER-UP/DOWN CHARACTERISTICS
PARAMETER CS , CEI , or WE at VIH before Power Fail VCCI Fall Time: VPF(MAX) to VPF(MIN) VCCI Fall Time: VPF(MIN) to VSO VCCI Rise Time: VPF(MIN) to VPF(MAX) VPF to RST High SYMBOL tPF tF tFB tR tREC MIN 0 300 10 0 40 200 TYP MAX UNITS ms ms ms ms ms NOTES
(TA = +25C)
PARAMETER Expected Data-Retention Time (Oscillator On) SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 6
CAPACITANCE
PARAMETER Capacitance on All Input Pins Capacitance on and DQ pins
IRQ , PWR , RST ,
(TA = +25C)
SYMBOL CIN CIO MIN TYP MAX 10 10 UNITS pF pF NOTES
AC TEST CONDITIONS
Output Load: Input Pulse Levels: 100pF + 1TTL Gate 0V to 3.0V for 5V operation
Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns
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DS1500
Figure 6. POWER-UP/DOWN WAVEFORM TIMING, 5V
VCCI VPF(MAX) VPF(MIN) VSO tPF RST tF tR t tDR tREC
tFB
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID VALID
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DS1500
Figure 7. WAKE-UP/KICKSTART TIMING DIAGRAM
Note: Time intervals shown above are referenced in the Wake-Up/Kickstart section.
WAKE-UP/KICKSTART TIMING
PARAMETER Kickstart-Input Pulse-Width Wake-Up/Kickstart Power-On Timeout SYMBOL tKSPW tPOTO MIN 2 2 TYP MAX
(TA = +25C)
UNITS ms s NOTES 5
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DS1500
NOTES:
1) Voltage referenced to ground. 2) Outputs are open. 3) The IRQ , PWR , and RST outputs are open drain. 4) Battery switchover occurs at the battery terminal-voltage level. 5) Wake-up/kickstart timeout generated only when the oscillator is enabled and the countdown chain is not reset. 6) tDR is specified with VCCO floating. If VCCO is powering an external SRAM, an auxiliary battery should be connected to the VBAUX pin. The auxiliary battery should be sized such that it can power the external SRAM for the tDR period. 7) Value for voltage and currents is from the VCCI input pin to the VCCO pin. 8) Value for voltage and currents is from the VBAT or VBAUX input pin to the VCCO pin. 9) IBAT1 and IBAT2 are specified with VCCO floating and do not include any RAM current. 10) These parameters are sampled with a 5pF load and are not 100% tested.
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